1. Field of the Invention
The present invention relates to an organic light emitting display and a method of driving the same.
2. Discussion of the Related Art
Recently, various flat panel displays (FPDs) having reduced weight and volume in comparison to cathode ray tubes (CRTs) have been developed. The FPDs include liquid crystal displays (LCDs), field emission displays (FEDs), plasma display panels (PDPs), and organic light emitting displays.
Among the FPDs, the organic light emitting displays display images using organic light emitting diodes (OLEDs) that generate light by re-combination of electrons and holes. The organic light emitting display has high response speed and is driven with low power consumption.
In general, the pixels of the organic light emitting display charge a predetermined voltage in a storage capacitor Cst included in each of the pixels and supply current corresponding to the charged voltage to the OLEDs to display an image (analog driving). However, in the above described method, it is difficult to display a uniform image due to variations of the threshold voltage and mobility of a driving transistor included in each of the pixels.
In order to solve the above problem, a digital driving method is provided. In the digital driving method, one frame is divided into a plurality of sub frames and the emission and non-emission of the pixels are controlled in each sub frame to display an image. For example, an emission period included in each of the plurality of sub frame periods included in one frame is increased in the ratio of 2n (n=0, 1, 2, 3, 4, 5, 6, and 7). In this case, the emission of the pixels is controlled in the emission period of each of the sub frames to display an image of predetermined gray levels.
In the digital driving method, the driving transistor included in each of the pixels is turned on or off to display gray levels. When the gray levels are realized using the turning on or off of the driving transistor, an image with uniform brightness can be displayed regardless of non-uniformity of the driving transistor.
In the digital driving method, since data are supplied to a data driver in units of sub frames, data are stored and output using a dual port memory. In more detail, the dual port memory stores data in response to a first clock from the outside and outputs the stored data in response to a second clock having a different frequency from the frequency of the first clock.
However, since one cell includes eight transistors in the dual port memory, cost and mounting area increase when an integrated circuit is realized. In order to solve the problem, a method of driving a conventional memory (a pseudo dual port memory (including six transistors in one cell)) together with the dual port memory is used. That is, data are stored and output while a first clock and a second clock are supplied to a memory.
However, when the conventional memory is used together with the dual port memory, collision (for example, read and write clocks can be supplied to the same cell) can be generated in reading and writing operations. In order to prevent such a phenomenon, a phase locked loop (PLL) is used. However, the circuit structure of the PLL is complicated and a large mounting area is occupied.